Figure 7
From: In silico design and in vivoimplementation of yeast gene Boolean gates
OR gates based on distributed output architecture. A) tet OR NOT(estr)–IMPLY logic function. B) tet OR IPTG. For both circuits, measured and expected fluorescence output levels are reported. Notice that YES tetOp gates inside both OR gates differ from the one in Table 1 since their plasmid vectors do not carry the HIS3 marker (see Additional file 1: Table S3, for more details).